联系方式：xianghonghu@gdut.edu.cn
通讯地址：理学馆609-4
所属团队：软硬件一体化研究团队
简介：
胡湘宏，特聘副教授，研究生导师，广东工业大学学士学位，广东工业大学博士学位，主要从事数字集成电路设计、AI芯片、信息安全芯片等研究。
研究方向：
1. 数字集成电路设计；
2. AI芯片；
3. 信息安全芯片;
教育经历：
2017/09-2020/06, 广东工业大学，控制科学与工程，工学博士
2015/09-2017/06, 广东工业大学，电路与系统，工学硕士
2011/09-2015/06, 广东工业大学，通信工程，工学学士
工作经历：
2021/02-2022/06，香港科技大学/智能晶片与系统研发中心ACCESS, 访问学者/博士后
2022/07-至今，广东工业大学，集成电路学院，讲师/特聘副教授
主要荣誉：
1. 新一代国密芯片及信息安全系统，广东省科技进步二等奖（排名第8），2020年
科研项目：
1. 面向边缘人工智能的混合位宽稀疏卷积神经网络加速器研究,国家自然科学基金青年基金, 2024.01-2026.12，30万元
2. 综合在线动态学习能力的网络优化技术及专用AI处理器设计，广州市科技计划项目（重点研发计划），2023.04.01-2026.03.31
3. 基于可重构和抗攻击技术的安全芯片研究，广东省基础与应用基础研究基金项目, 2022.10.01-2025.09.30，10万元
4. 国密算法IP设计与信息安全芯片研发，佛山市促进高校科技成果服务产业发展扶持项目(市外合作高校产学研项目导师团队补贴)，2020.12.23，10万元
科研成果：
1.代表性学术论文（第一作者/第一通讯）：
[1]. X. Hu , W. Zhuo , Q. Ye, Y. Lin , X. Li , H. Huang, R. Zhan , S. Cai* , and X. Xiong* "BAPE:A Binary or Ternary-Weights Transformer Accelerator Based on Precomputation at the Edge," in IEEE Transactions on Circuits and Systems I: Regular Papers, doi: 10.1109/TCSI.2026.3727987. Early Access, 2026.
[2]. Y. Lin, Z. Zhang, X. Li, H. Huang, H. Mai, R. Zhan, X. Hu*, S. Cai*, and X. Xiong, An FPGA-Efficient CNN Accelerator for Hybrid Model Compression with Scalable Bit-Serial and Bit-Parallel MAC, IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 73, no. 8, pp. 5528-5541, Aug. 2026, doi: 10.1109/TCSI.2026.3683559.
[3]. Y. Lin, K. Liang, P. Zhang, Z. Zhang, X. Li, H. Huang, R. Zhan, S. Cai*, X. Hu*, and X. Xiong, "An FPGA-Efficient CNN Accelerator by Integrating Value-Based Sparsity and Bit-Level Sparsity for Weight Compression," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2026.3652498.
[4]. X. Hu , Y. Liu , J. Li , Z. Zheng , X. Li , Y. Lin , H. Huang, R. Zhan , S. Cai *, and X. Xiong*. RVBSCop: A RISC-V-Based Coprocessor With 229.53 GOPS/W and 92.19 GOPS/mm for LLM Inference, IEEE Transactions on Very Large Scale Integration (VLSI) Systems,doi: 10.1109/TVLSI.2026.3733137. Early Access, 2026.
[5]. Y. Lin, P. Zhang, Z. Zhang, X. Li, H. Huang*, R. Zhan, X. Hu*, S. Cai, and X. Xiong, "Efficient FPGA Acceleration for 4-bit CNNs via Quantization-Induced Structured Sparsity and LUT-Based Multiplication," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 34, no. 5, pp. 1677-1681, May 2026, doi: 10.1109/TVLSI.2026.3663320.
[6]. X. Li, J. Pan, H. Huang, Y. Lin, X. Hu*, S. Cai, X. Xiong, An efficient DSP packing framework for FPGA-based mixed-precision DCNN processor. Journal of Systems Architecture, vol. 171, February 2026.
[7]. Y. Lin, P. Zhang , Y. Yu, Z. Zhang , X. Hu*, S. Cai, and X. Xiong*, "Hardware-Algorithm Co-Design for Efficient Bit-Serial Acceleration of Lightweight CNNs With Standard and Depthwise Convolutions on FPGA," in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 34, no. 9, pp. 2976-2988, Sept. 2026, doi: 10.1109/TVLSI.2026.3705608.
[8]. X. Hu, J. Li, Y. Liu, X. Li, Y. Lin , H. Huang, R. Zhan, S. Cai*, and X. Xiong*, CLPA: A Clustering-Based Low-Power Accelerator for Energy-Efficient Matrix Multiplication, in IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 34, no. 9, pp. 3065-3069, Sept. 2026, doi: 10.1109/TVLSI.2026.3706620.
[9]. Y. Lin, Z. Feng, X. Li, H. Huang, R. Zhan, X. Hu*, S. Cai *, and X Xiong. An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 11, pp. 1595-1599, Nov. 2025.
[10]. X. Hu*, X. Liu, Y. Liu, H. Zhang, X. Huang, X. Guan, L. Liang, C. Y. Tsui, X. Xiong, and K-T Cheng. A Tiny Accelerator for Mixed-bit Sparse CNN based on Efficient Fetch Method of SIMO SPad. IEEE Transactions on Circuits and Systems II: Express Briefs. 2023, 70(8): 3079-3083.
[11]. X. Zheng, S. Liang, B. Liu, X. Xiong, X. Hu*, Y. Liu*. Subgraph Feature Extraction based on Multi-View Dictionary Learning for Graph Classification, Knowledge-Based Systems, February 2021, vol. 214, 106716. doi: 10.1016/j.knosys.2020.106716.
[12]. X. Hu, C. Yang, X. Li, R. Li, Y. Lin, S. Fu, H. Huang, S. Cai*, X. Xiong*. A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees. ACM Transactions on Embedded Computing Systems, vol. 24, no. 6, pp. 1-26, 2025.
[13]. X. Hu, H. Huang, X. Li, X. Zheng*, Q. Ren, J. He, and X. Xiong*. High-Performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System. ACM Transactions on Embedded Computing Systems, 2023, 22(90):1–20.
[14]. Y. Lin, S. Fu, X. Li, C. Yang, R. Li, H. Huang, X. Hu*, S. Cai, and X. Xiong*. A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator," in IEEE Computer Architecture Letters, vol. 24, no. 1, pp. 65-68, 2025.
[15]. X. Hu, S. Fu, Y. Lin, X. Li, C. Yang, R. Li, H. Huang, S. Cai*, X. Xiong*. An FPGA-Based Bit-Level Weight Sparsity and Mixed-Bit Accelerator for Neural, Journal of Systems Architecture, vol. 166, no. C, 103463, 2025
[16]. X. Hu, Y. Lin, X. Li, R. Zhan, J. Cao, D. Zhu, S. Cai, X. Zheng*, and X. Xiong*. "A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency," in IEEE Computer Architecture Letters, vol. 24, no. 2, pp. 349-352, July-Dec. 2025,
[17]. X. Hu, J. Pan, Y. Ding, W. Huang, Z. Zheng, X. Li, H. Huang*, X. Xiong*. A High‐Efficiency CNN Accelerator With Mixed Low‐Precision Quantization. IET Circuits, Devices and Systems. 2025.
[18]. X. Hu, X. Li, H. Huang, X. Zheng*, X. Xiong*, TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2301-2305, April 2022, doi: 10.1109/TCSII.2022.3150980.
[19]. X. Hu , X. Li , X. Zheng, Y. Liu, X. Xiong*, A High Speed Processor for Elliptic Curve Cryptography over NIST Prime Field, IET Circuits, Devices and Systems, 2022, 16(4): 350-359, doi: 10.1049/cds2.12110.
[20]. X. Hu, T. Chen, H. Huang, Z. Liu, X. Li, X. Xiong*. Efficient Field-Programmable Gate Array-based Reconfigurable Accelerator for Deep Convolution Neural Network. Electronics Letter, IET, 2021, 57(6): 238-240, doi: 10.1049/ell2.12121.
[21]. X. Hu, H. Huang, X. Zheng, Y. Liu, and X. Xiong, Low-power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT, IEICE Transaction on Electronics, Vol.E104-C, No.11, pp. 643-650, Nov. 2021. doi: 10.1587/transele.2021ECP5009.
[22]. X. Li, H. Huang, Y. Liu, X. Hu*, X. Xiong*. A Digital Signal Processor-Efficient Accelerator for Depthwise Separable Convolution. Electronics Letter, doi: 10.1049/ell2.12435.
[23]. H. Huang, X. Hu*, X. Li, X. Xiong*. An Efficient Loop Tiling Framework for Convolutional Neural Network Inference Accelerators. IET Circuits, Devices and Systems, doi: 10.1049/cds2.12091.
2.知识产权：
1. 模约减方法、装置、设备及计算机可读存储介质, 胡湘宏;熊晓明;张盛仕;郑欣; 2021-03-16, ZL201810026230.3.
2. 一种基于物理不可克隆技术PUF的用户认证设备及认证方法与流程, 熊晓明; 张盛仕; 胡湘宏; 2020-12-11, ZL201810872171.1.
3. 一种基于PSoC的卷积神经网络加速器, 熊晓明;李子聪;曾宇航;胡湘宏; 2022-03-11, ZL201810689938.7.
4. 一种基于FPGA的支持8bit和16bit数据的可配置的CNN乘法累加器, 胡湘宏;李学铭;黄宏敏;陈淘生;刘梓豪;熊晓明; 2023-08-29, ZL202110382102.4,
