1. 数字集成电路设计；
2. AI芯片；
3. 信息安全芯片;
1. 新一代国密芯片及信息安全系统，广东省科技进步二等奖（排名第8），2020年
Y. Lin, K. Liang, P. Zhang, Z. Zhang, X. Li, H. Huang, R. Zhan, S. Cai*, X. Hu*, and X. Xiong, "An FPGA-Efficient CNN Accelerator by Integrating Value-Based Sparsity and Bit-Level Sparsity for Weight Compression," in IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, doi: 10.1109/TCAD.2026.3652498.
X. Li, J. Pan, H. Huang, Y. Lin, X. Hu*, S. Cai, X. Xiong, An efficient DSP packing framework for FPGA-based mixed-precision DCNN processor. Journal of Systems Architecture, vol. 171, February 2026.
Y. Lin, Z. Feng, X. Li, H. Huang, R. Zhan, X. Hu *, S. Cai *, and X Xiong.. An FPGA Accelerator With Efficient Weight Compression by Combining Bit-Level Sparsity and Mixed-Precision Quantization," in IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 72, no. 11, pp. 1595-1599, Nov. 2025.
Y. Lin, S. Fu, X. Li, C. Yang, R. Li, H. Huang, X. Hu*, S. Cai, and X. Xiong*. A DSP-Based Precision-Scalable MAC With Hybrid Dataflow for Arbitrary-Basis-Quantization CNN Accelerator," in IEEE Computer Architecture Letters, vol. 24, no. 1, pp. 65-68, 2025,
X. Hu, S. Fu, Y. Lin, X. Li, C. Yang, R. Li, H. Huang, S. Cai*, X. Xiong*. An FPGA-Based Bit-Level Weight Sparsity and Mixed-Bit Accelerator for Neural, Journal of Systems Architecture, vol. 166, no. C, 103463, 2025
X. Hu, C. Yang, X. Li, R. Li, Y. Lin, S. Fu, H. Huang, S. Cai*, X. Xiong*. A Precision-Scalable Accelerator with Sign-Magnitude Representation and Dual Adder Trees. ACM Transactions on Embedded Computing Systems, vol. 24, no. 6, pp. 1-26, 2025.
X. Hu, Y. Lin, X. Li, R. Zhan, J. Cao, D. Zhu, S. Cai, X. Zheng*, and X. Xiong*. "A Multiple-Aspect Optimal CNN Accelerator in Top1 Accuracy, Performance, and Power Efficiency," in IEEE Computer Architecture Letters, vol. 24, no. 2, pp. 349-352, July-Dec. 2025,
X. Hu, J. Pan, Y. Ding, W. Huang, Z. Zheng, X. Li, H. Huang*, X. Xiong*. A High‐Efficiency CNN Accelerator With Mixed Low‐Precision Quantization. IET Circuits, Devices and Systems. 2025.
X. Hu*, X. Liu, Y. Liu, H. Zhang, X. Huang, X. Guan, L. Liang, C. Y. Tsui, X. Xiong, and K-T Cheng. A Tiny Accelerator for Mixed-bit Sparse CNN based on Efficient Fetch Method of SIMO SPad. IEEE Transactions on Circuits and Systems II: Express Briefs. 2023, 70(8): 3079-3083.
X. Hu, X. Li, H. Huang, X. Zheng*, X. Xiong*, TiNNA: A Tiny Accelerator for Neural Networks With Efficient DSP Optimization, IEEE Transactions on Circuits and Systems II: Express Briefs, vol. 69, no. 4, pp. 2301-2305, April 2022, doi: 10.1109/TCSII.2022.3150980.
X. Hu, H. Huang, X. Li, X.*, Q. Ren, J. He, and X. Xiong*. High-Performance Reconfigurable DNN Accelerator on a Bandwidth-limited Embedded System. ACM Transactions on Embedded Computing Systems, 2023, 22(90):1–20.
X. Hu , X. Li , X. Zheng, Y. Liu, X. Xiong*, A High Speed Processor for Elliptic Curve Cryptography over NIST Prime Field, IET Circuits, Devices and Systems, 2022, 16(4): 350-359, doi: 10.1049/cds2.12110.
X. Hu, T. Chen, H. Huang, Z. Liu, X. Li, X. Xiong*. Efficient Field-Programmable Gate Array-based Reconfigurable Accelerator for Deep Convolution Neural Network. Electronics Letter, IET, 2021, 57(6): 238-240, doi: 10.1049/ell2.12121.
X. Hu, H. Huang, X. Zheng, Y. Liu, and X. Xiong, Low-power Reconfigurable Architecture of Elliptic Curve Cryptography for IoT, IEICE Transaction on Electronics, Vol.E104-C, No.11, pp. 643-650, Nov. 2021. doi: 10.1587/transele.2021ECP5009.
X. Li, H. Huang, Y. Liu, X. Hu*, X. Xiong*. A Digital Signal Processor-Efficient Accelerator for Depthwise Separable Convolution. Electronics Letter, doi: 10.1049/ell2.12435.
H. Huang, X. Hu*, X. Li, X. Xiong*. An Efficient Loop Tiling Framework for Convolutional Neural Network Inference Accelerators. IET Circuits, Devices and Systems, doi: 10.1049/cds2.12091.
X. Zheng, S. Liang, B. Liu, X. Xiong, X. Hu*, Y. Liu*. Subgraph Feature Extraction based on Multi-View Dictionary Learning for Graph Classification, Knowledge-Based Systems, February 2021, vol. 214, 106716. doi: 10.1016/j.knosys.2020.106716.
